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Description: verilog写双端口存储器模型-a Model of Writing Double-Port RAM developed with Verilog
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Size: 1067 |
Author: 杨艳 |
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Description: Capacity RAM Model的VHDL的例子。最佳的资源优化版。-Capacity Model RAM VHDL example. The best resource optimization version.
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Size: 3514 |
Author: 周阳 |
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Description: verilog写双端口存储器模型-a Model of Writing Double-Port RAM developed with Verilog
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Size: 1024 |
Author: 杨艳 |
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Description: Capacity RAM Model的VHDL的例子。最佳的资源优化版。-Capacity Model RAM VHDL example. The best resource optimization version.
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Size: 3072 |
Author: 周阳 |
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Description: Synthesizable FIFO Model
This example describes a synthesizable implementation of a FIFO. The FIFO depth and FIFO width in bits can be modified by simply changing the value of two parameters, `FWIDTH and `FDEPTH. For this example, the FIFO depth is 4 and the FIFO width is 32 bits.
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Size: 16384 |
Author: lianlianmao |
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Description: fpga中ram的vhdl的经典程序,适用于ALTERA公司器件-FPGA in VHDL ram the classic procedure, applicable to the company ALTERA devices
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Size: 1024 |
Author: gcy |
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Description: 双口RAM的应用-Application of dual-port RAM
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Size: 168960 |
Author: puppy |
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Description: 基于altera ep2c8双口RAM -Altera ep2c8-based dual-port RAM
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Size: 884736 |
Author: 秦学富 |
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Description: dsp 28335 源程序代码,用来测试RAM模式和flash模式 DSP-the program is used to test the RAM model and Flash model for dsp 28335 from TI
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Size: 2790400 |
Author: lilienthal |
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Description: 用于仿真的现代RAM HY57V561620IBIS-RAM HY57V561620 IBIS model
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Size: 16384 |
Author: 张旭 |
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Description: This program was produced by
PHM-123
Chip type : ATmega16
Program type : Application
AVR Core Clock frequency: 16.000000 MHz
Memory model : Small
External RAM size : 0
Data Stack size : 256-This program was produced by
PHM-123
Chip type : ATmega16
Program type : Application
AVR Core Clock frequency: 16.000000 MHz
Memory model : Small
External RAM size : 0
Data Stack size : 256
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Size: 166912 |
Author: mahaseni |
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Description: 该源码包是2.0版本的AMBA总线的Verilog语言模型,主要包括5个部分:AHB总线仲裁器,AHB-APB总线桥接器,AHB总线上从设备ROM模型,AHB总线上从设备RAM模型,参数定义。-This source code package is the model of V2.0 AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_Rom_Slave, AHB_Ram_Slave,Defines.
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Size: 17408 |
Author: jinjin |
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Description: AD9954驱动程序,主控为CPU为STM32,包括单一模式,线性扫面模式,RAM模式,可以产生AM,FM,ASK,PSK,FSK调制信号-AD9954 driver, master for CPU is STM32, including single mode, linear sweep surface model, RAM model, can generate AM, FM, ASK, PSK, FSK modulation signal
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Size: 3072 |
Author: 亮 |
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Description: onida dvd mt 1389,de, 54pin ram onida dvd
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Size: 946176 |
Author: pramod |
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Description: the PRAM model is an extension of the familiar
RAM model of sequential computation that is used in algorithm analysis. We will use the synchronous PRAM which
is defined
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Size: 1419264 |
Author: thanhtung0601 |
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Description: the PRAM model is an extension of the familiar
RAM model of sequential computation that is used in algorithm analysis. We will use the synchronous PRAM which
is defined
Platform: |
Size: 589824 |
Author: thanhtung0601 |
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Description: the PRAM model is an extension of the familiar
RAM model of sequential computation that is used in algorithm analysis. We will use the synchronous PRAM which
is defined
Platform: |
Size: 45056 |
Author: thanhtung0601 |
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Description: the PRAM model is an extension of the familiar
RAM model of sequential computation that is used in algorithm analysis. We will use the synchronous PRAM which
is defined
Platform: |
Size: 687104 |
Author: thanhtung0601 |
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Description: 通过merge-sort算法的实现,掌握外存算法所基于的I/O模型与内存算法基于的RAM模型的区别;理解不同的磁盘访问优化方法是如何提高数据访问性能的。-Merge-sort algorithm, to grasp the core algorithm based I/O model memory algorithm is based on the distinction RAM model understand how different disk access optimization method to improve data access performance.
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Size: 120832 |
Author: |
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Description: 这个程序是DSP28335 应用DMA与RAM通信的程序,可以实现28335与RAM之间的快速通信-this is a program of DSP 28335 DAM and RAM model
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Size: 48128 |
Author: 梁满囤 |
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